1. Field of the Invention
The present invention relates generally to a system and method for interfacing the timing control between components in a computer based system. More particularly, the present invention relates to a system and method for isolating the timing domain of a CPU from the timing domain of a memory bus.
2. Related Art
In conventional computer systems, processor speed is constrained by memory bus speed. Memory bus speeds are generally slower than top processor speeds today. When a processor shares a bus with its associated memory, the maximum operating speed is limited to the speed of the slowest component, the memory.
With the fast pace of today's computer system design cycles, technology improvements, and continuously increasing performance goals, it has become desirable to upgrade or modify existing computer systems in a timely and cost effective manner. In the design of high performance computer systems, a central processing unit (CPU) is usually the target for providing the greatest improvements in performance levels, and the operating speed of the CPU is usually constrained to that of peripheral devices which may be connected to it. It is now possible and desirable to design a CPU integrated circuit which operates at much faster speeds than existing peripheral devices. Furthermore, it is desirable to design the CPU such that it can operate at a number of different speed ratios so that it may be used in several different computer system configurations.
Current computer systems which implement components operating at differing clock frequencies are restricted to operating such components only at frequency ratios of N:1, where N is a fixed positive integer. Such prior systems also relied on complex general synchronizers to coordinate data transfers between components.
What is needed is a system and method for allowing the CPU and memory to operate transparently and interchangeably at frequency ratios of N:M, (where N and M are integers, with N greater than or equal to M) to take advantage of non-integer multiples of processor to memory bus speed. In general, what is needed is a system where CPU clock speed need not be constrained by the operating speed of a peripheral device.